{"id":153201,"date":"2008-02-01T00:00:00","date_gmt":"2008-02-01T00:00:00","guid":{"rendered":"https:\/\/newed.any0.dpdns.org\/en-us\/research\/msr-research-item\/enhancing-the-performance-and-fairness-of-shared-dram-systems-with-parallelism-aware-batch-scheduling\/"},"modified":"2018-10-16T21:08:14","modified_gmt":"2018-10-17T04:08:14","slug":"enhancing-the-performance-and-fairness-of-shared-dram-systems-with-parallelism-aware-batch-scheduling","status":"publish","type":"msr-research-item","link":"https:\/\/newed.any0.dpdns.org\/en-us\/research\/publication\/enhancing-the-performance-and-fairness-of-shared-dram-systems-with-parallelism-aware-batch-scheduling\/","title":{"rendered":"Enhancing the Performance and Fairness of Shared DRAM Systems with Parallelism-Aware Batch Scheduling"},"content":{"rendered":"<div class=\"asset-content\">\n<p>In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by causing bank\/bus\/row-buffer conflicts but they can also destroy other threads&#8217; DRAM-bank-level parallelism. Requests whose latencies would otherwise have been overlapped could effectively become serialized. As a result both fairness and system throughput degrade, and some threads can starve for long time periods. This paper proposes a fundamentally new approach to designing a shared DRAM controller that provides quality of service to threads, while also improving system throughput. Our parallelism-aware batch scheduler (PAR-BS) design is based on two key ideas. First, PAR-BS processes DRAM requests in batches to provide fairness and to avoid starvation of requests. Second, to optimize system throughput, PAR-BS employs a parallelism-aware DRAM scheduling policy that aims to process requests from a thread in parallel in the DRAM banks, thereby reducing the memory-related stall-time experienced by the thread. PAR-BS seamlessly incorporates support for system-level thread priorities and can provide different service levels, including purely opportunistic service, to threads with different priorities. We evaluate the design trade-offs involved in PAR-BS and compare it to four previously proposed DRAM scheduler designs on 4-, 8-, and 16-core systems. Our evaluations show that, averaged over 100 4-core workloads, PAR-BS improves fairness by 1.11X and system throughput by 8.3% compared to the best previous scheduling technique, Stall-Time Fair Memory (STFM) scheduling. Based on simple request prioritization rules, PAR-BS is also simpler to implement than STFM.<\/p>\n<\/div>\n<p><!-- .asset-content --><\/p>\n","protected":false},"excerpt":{"rendered":"<p>In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by causing bank\/bus\/row-buffer conflicts but they can also destroy other threads&#8217; DRAM-bank-level parallelism. Requests whose latencies would otherwise have been overlapped could effectively become serialized. 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