{"id":160977,"date":"2011-05-01T00:00:00","date_gmt":"2011-05-01T00:00:00","guid":{"rendered":"https:\/\/newed.any0.dpdns.org\/en-us\/research\/msr-research-item\/tmbox-a-flexible-and-reconfigurable-16-core-hybrid-transactional-memory-system\/"},"modified":"2018-10-16T20:59:45","modified_gmt":"2018-10-17T03:59:45","slug":"tmbox-a-flexible-and-reconfigurable-16-core-hybrid-transactional-memory-system","status":"publish","type":"msr-research-item","link":"https:\/\/newed.any0.dpdns.org\/en-us\/research\/publication\/tmbox-a-flexible-and-reconfigurable-16-core-hybrid-transactional-memory-system\/","title":{"rendered":"TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System"},"content":{"rendered":"<div class=\"asset-content\">\n<p>In this paper we present the design and implementation of TMbox: An MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTMASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.<\/p>\n<\/div>\n<p><!-- .asset-content --><\/p>\n","protected":false},"excerpt":{"rendered":"<p>In this paper we present the design and implementation of TMbox: An MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. 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